A MOS type circuit has a feature that it consumes a current only when an active element therein inverts its state, while there flows merely infinitesimal current such as a current flowing through an insulation resistance or so when all of active elements are in their quiescent state.
A testing method has been heretofore known, which comprises the steps of measuring a power supply current flowing through a semiconductor integrated circuit element constructed by a MOS type circuit in its quiescent state, and determining the presence of a short-circuit failure or an open-circuit failure in the semiconductor integrated circuit element depending on whether the measured value of the power supply current is greater than a prescribed value or not, thereby determining whether the semiconductor integrated circuit element has a defect or not.
FIG. 4 shows an example of the conventional testing method. An IC under test 11 has a power supply terminal 11A connected to a power supply circuit 12 which in turn supplies to the power supply terminal 11A a power supply voltage Vdd which has been prescribed for the IC under test 11, and a power supply terminal 11B of the IC under test 11 through which a current flows out of the IC under test 11 is connected to a common potential point COM.
The power supply circuit 12 comprises an operational amplifier 12A, and a digital-to-analog (D/A) converter 12B operating as a voltage source, which is arranged to be capable of supplying a current I.sub.P (see FIG. 5) consumed in a pulse-like manner by the IC under test 11 without any delay.
Specifically, a voltage which is the same as the voltage Vdd to be applied to the power supply terminal 11A of the IC under test 11 is applied from the D/A converter 12B to the non-inverting input terminal of the operational amplifier 12A. An output terminal of the operational amplifier 12A is connected through a current measurement means 13 to a sensing point SEN, thereby to apply the power supply voltage Vdd to the power supply terminal 11A of the IC under test 11 through the sensing point SEN as well as to feed a voltage at the sensing point SEN back to the inverting input terminal of the operational amplifier 12A.
With the above circuit construction of the power supply circuit 12, by generating the power supply voltage Vdd to the IC under test 11 from the D/A converter 12B to supply the voltage Vdd to the non-inverting input terminal of the operational amplifier 12A, the operational amplifier 12A performs a feedback operation such that the voltage V1 at the sensing point SEN coincides with the voltage Vdd applied to the non-inverting input terminal of the operational amplifier 12A, and this feedback operation continues to supply the voltage Vdd to the power supply terminal 11A of the IC under test 11.
A current detecting resistor Ri is connected between the output terminal of the operational amplifier 12A and the sensing point SEN, and a voltage produced across the current detecting resistor Ri is measured, thereby to measure a current Idd passing through the IC under test 11. In this example, a measurement of the current Idd (see FIG. 5) when the IC under test 11 is in its quiescent state will be described. Since the current Idd which flows under the quiescent state is of the order of several micro-amperes (.mu.A) to several tens of .mu.A, the resistance of the current detecting resistor Ri will be as high as the order of 100 kilohms (k.omega.). Accordingly, two diodes D1 and D2 are connected in parallel with the current detecting resistor Ri to bypass the current I.sub.P that flows when the IC under test 11 is turned to be operative.
A voltage produced by the current Idd flowing through the current detecting resistor Ri is at most of the order of several tens of millivolts (mV). Accordingly, within a range of voltages produced by the current Idd to be measured, the diodes D1 and D2 maintain their off state. The voltage produced across the current detecting resistor Ri is taken out by a subtraction circuit 13A and given to an output terminal 13B. The voltage V.sub.M supplied to the output terminal 13B undergoes an analog-to-digital (A/D) conversion in an A/D converter, for example, and the current Idd is calculated or computed from the value of the voltage V.sub.M. If the calculated current Idd is greater than a prescribed value, that IC is determined to be defective (failure) or non-conforming article. The measurement of the current Idd is carried out by inputting a test pattern signal to input terminals 11C of the IC under test 11 and setting the inside of the IC to various quiescent modes, and if the measured values of the current Idd are less than the prescribed value in all of the quiescent modes, the IC is determined to be conforming or pass article.
As noted, this power supply circuit 12 consumes the current I.sub.P in a pulse-like manner when the IC under test 11 is turned to be operative. Though the current I.sub.P is supplied from the power supply circuit 12 constituted by the operational amplifier 12A, a delay or lag is produced in a response of the operational amplifier 12A because a large current (several mA to several tens of mA) flows transiently through the operational amplifier 12A. For this reason, a technique or procedure has been adopted, which connects a smoothing capacitor C1 having a relatively large capacitance to the output side of the power supply circuit 12, thereby to compensate for a reduction in the voltage/current accompanied by the response lag of the power supply circuit 12.
As discussed above, the necessity of connecting the smoothing capacitor C1 having a large capacitance results in that when there occurs any slight noise at the sensing point SEN, a noise current I.sub.c1 flows through the smoothing capacitor C1. Since the noise current I.sub.c1 is supplied from the current measurement means 13, it may interfere with the measurement of the current Idd.
Consequently, the recent trend is toward use of a technique or procedure as shown in FIG. 6 in which a current detecting resistor Ri is connected between the power supply terminal 11B of the IC under test 11 through which any current flow is taken out of the IC under test 11 and a point of common potential (COM), and a voltage produced across this current detecting resistor Ri is measured, thereby to calculate or compute the current Idd.
In this case, a short-circuit switch 14 is connected in parallel with the current detecting resistor Ri. This short-circuit switch 14 is controlled to turn on upon an inverting operation of the IC under test 11, and a large current I.sub.P occurring at that time is to be bypassed through the short-circuit switch 14. For this end, a transistor called DMOS or the like is used as the short-circuit switch 14, the transistor being capable of operating at a high-speed and yet exhibiting a low resistance when it turns on.
With the circuit construction shown in FIG. 6, the quiescent current Idd (current flow in quiescent state of the IC under test) hardly changes even if there is some variation in the power supply voltage, provided that the voltage of the power supply circuit 12 remains at a voltage equal to or higher than a fixed value. In other words, there is obtained an advantage that the quiescent current Idd can be measured in a stable condition without being influenced by the noise current passing through the smoothing capacitor C1.
On the other hand, however, if a relatively large current should flow through the current detecting resistor Ri due to that the short-circuit switch 14 turning off too early timing or that a short-circuit failure or the like occurs within the IC under test 11, thereby to produce the current Idd which is larger than the prescribed value, or the like, a high voltage is produced across the current detecting resistor Ri to raise the voltage at the power supply terminal 11B through which any current flow is taken out of the IC 11, resulting in a possibility of causing a malfunctioning of the IC under test 11. In addition, if a wiring used to connect the short-circuit switch 14 has an inductance component, there is a possibility that the flow of a pulse-like current of a substantial magnitude through the inductance component may produce a spike noise, which results in a damage to the IC under test 11. For this reason, an arrangement is such that a diode D3 is connected in parallel with the current detecting resistor Ri, thereby to prevent the voltage at the power supply terminal 11B from abnormally rising due to a spike noise or the like.
Moreover, when the diode D3 is connected in such manner, there is a disadvantage that since a diode generally has an off capacitance component due to the PN junction thereof (a capacitance when the diode is in off state), if a spike current is charged in the off capacitance of the diode D3 by a noise voltage or the like under the off state of the short-circuit 14, the discharge path of the off capacitance of the diode D3 will be only the current detecting resistor Ri, which results in a long discharge time duration needed by the diode D3. Stated differently, the measurement of the current Idd must be done after the discharge of the diode D3 has completed, resulting in a drawback that it takes much time duration to measure the current Idd.
It is an object of the present invention to provide an IC testing apparatus which is capable of eliminating above-mentioned disadvantages, and measuring a quiescent current Idd of an IC under test flowing therethrough when the IC is in its quiescent state safely and at high-speed, thereby to determine whether the IC is conforming (pass) or non-conforming (failure) article.